Standard Cell Layout With Regular Contact Placement

Optimal decoupling capacitor sizing and placement for standard-cell layout designs

With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The ad...

Digital Layout - Placement

VLSI: Techniques for Efficient Standard Cell Placement

In the physical designing of the chip, placement is one of the most important steps in the design flow, this paper gives the basic overview of the placement algorithms being used with shrinking technology node for the automatic placement of cells which gives an optimized design in terms of chip area, speed and cost. Basically the emphasis will be on recent trends of Wire-length driven placement...

An Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques

In recent years, size of VLSI circuits is dramatically grown and layout generation of current circuits has become a dominant task in design flow. Standard cell placement is an effective stage of physical design and quality of placement affects directly on the performance, power consumption and signal immunity of design. Placement can be performed analytically or heuristically. Analytical placer...

Optimal End-Case Partitioners and Placers for Standard-Cell Layout

We develop new optimal partitioning and placement codes for end-case processing in top-down standard-cell placement. Such codes are based on either enumeration or branch-and-bound, and are invoked for instances below prescribed size thresholds (e.g., < 30 cells for partitioning, or < 10 cells for placement). Our optimal partitioners handle tight balance constraints and uneven cell sizes transpa...